Integrated circuits are typically formed on substrates, particularly silicon wafers, by the sequential deposition of conductive, semiconductive or insulative layers. After a layer is deposited, a photoresist coating is applied on top of the layer. A photolithographic apparatus, which operates by focusing a light image on the coating, is used to remove predetermined portions of the coating, leaving the photoresist coating on areas where circuitry features are to be formed. The substrate is then etched to remove the uncoated portions of the layer, leaving the desired circuitry features.
As a series of layers are sequentially deposited and etched, the outer or uppermost surface of the substrate, becomes increasingly non-planar. This non-planar surface presents problems in the photolithographic steps of the integrated circuit fabrication process. Specifically, the photolithographic apparatus may not be able to focus the light image on the photoresist layer if the maximum height difference between the peaks and valleys of the non-planar surface exceeds the depth of focus of the apparatus. Therefore, there is a need to periodically planarize the substrate surface.
Chemical mechanical polishing (CMP) is one accepted method of planarization. Chemical mechanical polishing typically requires mechanically abrading the substrate in a slurry that contains a chemically reactive agent. During polishing, the substrate is typically held against a rotating polishing pad by a carrier head. The carrier head may also rotate and move the substrate relative to the polishing pad. As a result of the motion between the carrier head and the polishing pad, abrasives, which may either be embedded in the polishing pad or contained in the polishing slurry, planarize the non-planar substrate surface by abrading the surface.
The polishing process generates vibrations that may reduce the quality of the planarization or damage the polishing apparatus.